Hex Buffer/Converter IC - CD4010 The CD4010C hex buffers IC are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge. These gates may be used as hex buffers, CMOS to DTL or TTL interface or as CMOS current drivers. Conversion ranges are from 3V to 15V providing VCC ? VDD. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. The CD4x Series CD4010 Hex Buffer/Converters may be used as CMOS to TTL or DTL logic-level converters or CMOS high-sink-current drivers. The CD4010 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), and 16-lead dual-in-line plastic packages (E suffix). check out : CD4050 - Hex Non-Inverting Buffer IC Applications: CMOS to DTL/TTL hex converter CMOS current "sink" or "source" driver CMOS high-to-low logic-level converter Multiplexer — 1 to 6 or 6 to 1

CD4013 - Dual D Type Flip-Flop IC The CD4013 designed as a CMOS logic chip IC belongs to the CD4XXX IC series. The CD4013 device comprises two identical, independent data-type flip-flops. Each flip-flop comes with independent data, set, reset, and clock inputs, and Q and Q’ outputs. These devices are commonly used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transmitted to the Q output during the positive-going transition of the clock pulse. Moreover, the Setting or resetting of IC is independent of the clock and accomplished by a high level on the set or reset line, respectively.  The CD4013B is manufactured in 14-pin dual-inline plastic packages (E suffix), 14-pin small-outline packages (M, MT, M96, and NSR suffixes), and 14-pin thin shrink small-outline packages (PW and PWR suffixes). A D-type Latch/flip-flop is designed as a clocked latch that has two stable states. A D-type latch operates with a delay in input by one clock cycle. Thus, by cascading many D-type flip-flops delay circuits are often created, which are utilized in many applications like in digital television systems.  A D-type flip-flop is additionally mentioned as a D flip-flop or a delay flip-flop. The D flip-flop is an edge-triggered device that transfers input files to Q on a clock rising or falling edge. Data Latches are level sensitive devices like the data latch and therefore the transparent latch. Applications Power Delivery Grid Infrastructure Medical, Healthcare, and Fitness Body Electronics and Lighting Building Automation Telecom Infrastructure Test and Measurement

CD4016 - Quad Bilateral Switch IC The CD4x Series CD4016 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066B. The CD4016 is a CMOS IC with four analog switches, which can be controlled individually using a control pin. The signal can flow in either direction between the two pins of each switch. Each switch has an enable pin (A) and two input/output pins (X and Y). When the enable pin is set to HIGH, current can flow between X and Y in either direction. However, when enable is LOW, no current can flow between the pins. Just like a switch. Pinout: Pinout of CD4016 IC Pin Name Pin # Type Description VDD 14 Power Supply Voltage (+3 to +15V) GND 7 Power Ground (0V) A1-A4 5,6,12,13 Input Enable pins for the four bilateral switches X1-X4 1,3,9,11 Input/Output Pin X for each switch Y1-Y4 2,4,8,10 Input/Output Pin Y for each switch

8-bit Up/Down Binary Counter IC - CD40193 The CD40193 IC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BM and CD40192BC are BCD counters, while the CD40193BM and CD40193BC are binary counters. Counting up and counting down is performed by two count inputs, one being held high while the other is clocked. The outputs change on the positive-going transition of this clock. These CD4x Series IC counters feature preset inputs that are enabled when the load is a logical ‘‘0’’ and a clear which forces all outputs to ‘‘0’’ when it is at a logical ‘‘1’’. The counters also have to carry and borrow outputs so that they can be cascaded using no external circuitry. All inputs are protected against damage due to static discharge by clamps to VDD and VSS. check out : Divide by 8 Counter/Divider IC - CD4022 Pinout: Pinout of CD40193 IC Application Up/Down difference counting Multistage ripple counting Synchronous frequency divider A/D or D/A conversion BCD counting

14 Stage Ripple Carry Binary Counter IC - CD4020 The CD4020 IC is a ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all-zeros state. Schmitt's trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4x Series CD4020 type is supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). check out : CD4040 - 12-Stage Ripple Carry Binary Counter IC Pinout: Pinout of CD4020 IC Applications: Control counters Timers Frequency dividers Time-delay circuits

Decade Counter/Divider IC - CD4026 The CD4x Series CD4026 consists of a 5-stage Johnson decade counter and an output decoder that converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026 include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. A high RESET signal clears the decade counter to its zero counts. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (C out ) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven-segment display device used for representing the decimal numbers 0 to 9. The CD4026  outputs go high only when the DISPLAY ENABLE IN is high. The CD4026 series type is supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). check out : CD4033 - 5-Stage Johnson Decade counter IC Pinout: Pinout of CD4026 Decade IC Applications: Decade counting 7-segment decimal display Frequency division 7-segment decimal displays Clocks, watches, timers (e.g. ÷60, ÷60, ÷ 12 counter/display) Counter/display driver for meter applications

CD4029 - Binary Decade Up-Down Counter IC The CD4029 IC consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4, and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero counts. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRE-SET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel clocking or a ripple-clocking arrangement as shown in Figure 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4x Series CD4029 is supplied in these 16-lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W. Pinout: Pinout of CD4029 IC

CD4040 - 12-Stage Ripple Carry Binary Counter IC The CD4x Series CD4040 is a ripple-carry binary counter that features 12 stages, push-pull type, and balanced outputs, with standard speed (TPD > 50ns). All counter stages are master-slave flip-flops. Supports wide input voltage ranges from 3V to 18V. The maximum input current at 18V is 1 uA whereas 100 nA at 18V and 25°C. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all-zeros state. Schmitt's trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. 16 Pin DIP is available in a hermetic dual-in-line ceramic package. We also have a CD4020 with similar features. The differences are CD4020 is a 14 Stage binary counter whereas CD4040 is a 12 Stage binary counter and there is a difference between the pin layout. check out : CD4518 - Dual BCD Up Counter IC (Original) Pinout: Pinout of CD4040 IC Applications: Control Counters Timers Frequency Dividers Time-Delay Circuits

CD4049 - Hex Inverting Buffer/Converter IC The CD4x Series CD4049 hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. These devices feature logic-level conversion using only one supply voltage (VDD). The input signal level can exceed the VDD supply voltage when these devices are used for logic-level conversions. These devices are intended for use as hex buffers, CMOS to DTL/TTL converters, or as CMOS current drivers, and at VDD=5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range. check out : CD4504 - Hex Voltage Level Shifter IC Pinout: Pinout Of CD4049 IC Pin Name Pin # Type Description VDD 1 Power Supply Voltage (+3 to +15V) GND 8 Power Ground (0V) Q1-Q6 2, 4, 6, 10, 12, 15 Input Inputs to the inverters A1-A6 3, 5, 7, 9, 11, 14 Output Outputs from the inverters NC 13, 16 – Not Connected Applications: CMOS hex inverter/buffer CMOS to DTL/TTL hex converter CMOS current "sink" or "source" driver CMOS high-to-low logic level converter

CD4053 - Triple 2-channel Multiplexer/Demultiplexer IC The CD4053 IC analog multiplexers demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3?15V. For example, if VDD = 5V, VSS = 0V and VEE = ?5V, analog signals from ?5V to +5V can be controlled by digital inputs of 0?5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD?VSS and VDD?VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. The CD4x Series CD4053 Integrated Circuits is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels that are connected in a single-pole double-throw configuration. Pinout: Pin No Pin Name Description 1 Y1 Y1 Switch Input/Output 2 Y0 Y0 Switch Input/Output 3 Z1 Z1 Switch Input/Output 4 Z Input/Output Z 5 Z0 Z0 Switch Input/Output 6 INH Inhibit Input 7 VEE Emitter supply 8 VSS Source Supply 9 C Digital Control Input C 10 B Digital Control Input B 11 A Digital Control Input A 12 X0 X0 Switch Input/Output 13 X1 X1 Switch Input/Outputs 14 X Input/Output X 15 Y Input/Output Y 16 VDD Drain supply Applications: Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating