CD4033 - 5-Stage Johnson Decade counter IC The CD4033 IC consists of a 5-stage Johnson decade counter IC and an output decoder that converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g).  Signals peculiar to the CD4033 are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT. A high RESET signal clears the decade counter to its zero counts. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Anti-lock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (C out ) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven-segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the CD4033. The CD4033 series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). Pinout: Pinout of CD4033 - 5-Stage Johnson Decade counter IC Pin 1 known as Clock in – It receives clock signals, and at every positive clock counter advances one by one. You can provide a clock with the switch, 555 timer or the help of logic gates. Pin 2 known as Clock inhibit –  CD4033 counter advances one by one by receiving a positive pulse at this time clock inhibit pin should be grounded. If it is connected to the supply then counter advancement will be inhibited means there will be no meaning of clock pulse. Pin 3 and pin 4 known as Ripple blanking in and Ripple blanking – It is used to display only one zero blanking the other zero. For this IC have ripple blanking in and ripple blanking out. For example, you want to display 345 and you are using five 7 segment display then it will display 00345 if blanking input and out is off. But if it is on then you will receive 345. It improves the readability of the circuit. Pin 5 known as carry out – It is used to complete one cycle for every 10-clock input cycle and it is also used to cascade more ICs. Pin 6, pin7 and Pin9 to pin 13 – These are 7 decoded outputs from a to g used to illuminate the corresponding segment of 7 segment display to display the digit from 0 to 9. Pin 14 known as Lamp test –  t is used to check whether all segments of 7 segment is working properly or not. For testing momentarily make the pin low. Pin 15 known as Reset – It is used to reset the counter. When it receives high it clears the counter and counting again starts from zero. One important thing reset pin should again made low to start the counter once again. Pin 8 known as ground pin and Pin 16 known as Vdd it should be connected to power supply. Applications: Decade counting 7-segment decimal display Frequency division 7-segment decimal displays Clocks, watches, timers (e.g. ÷60, ÷60, ÷ 12 counter/display) Counter/display driver for meter applications check out : CD4060 - 14 stage Ripple Carry Binary Counter IC

CD4034 - 8-Stage Bidirectional Bus Register IC The CD4034 Register IC is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) Bi-directionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Input that controls the operations includes a single-phase CLOCK (CL), A-DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. Register expansion can be accomplished by simply cascading CD4034 packages. The CD4034 types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes). Pinout: Pinout of CD4034 - 8-Stage Bidirectional Bus Register IC Applications: Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register Shift right/shift-left register Shift right/shift left with parallel loading Address register Buffer register Bus system register with enable parallel lines at bus side Double bus register system Up-Down Johnson or ring counter Pseudo-random code generators Sample and hold register (storage, counting, display) Frequency and phase comparator

CD4040 - 12-Stage Ripple Carry Binary Counter IC The CD4x Series CD4040 is a ripple-carry binary counter that features 12 stages, push-pull type, and balanced outputs, with standard speed (TPD > 50ns). All counter stages are master-slave flip-flops. Supports wide input voltage ranges from 3V to 18V. The maximum input current at 18V is 1 uA whereas 100 nA at 18V and 25°C. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all-zeros state. Schmitt's trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. 16 Pin DIP is available in a hermetic dual-in-line ceramic package. We also have a CD4020 with similar features. The differences are CD4020 is a 14 Stage binary counter whereas CD4040 is a 12 Stage binary counter and there is a difference between the pin layout. check out : CD4518 - Dual BCD Up Counter IC (Original) Pinout: Pinout of CD4040 IC Applications: Control Counters Timers Frequency Dividers Time-Delay Circuits

CD4046 - Micropower Phase Locked Loop IC CD4046 CMOS Micropower Phase-Locked Loop (PLL) IC consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V Zener diode is provided for supply regulation if necessary. The CD series CD4046 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). check out : Dual JK Flip Flop IC - CD4027 Pinout: Pinout of CD4046 IC Applications: FM demodulator and modulator Frequency synthesis and multiplication Frequency discriminator Data synchronization Voltage-to-frequency conversion Tone decoding FSK - Modems Signal conditioning

CD4047 - Astable/Monostable Multivibrator IC CD4047 IC consists of a gateable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE\, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q\, Q an OSCILLATOR. In all modes of operation, an external capacitor must be connected between C-Timing and RC-Common terminal, and an external resistor must be connected between the R-Timing and RC-Common terminals. Astable operation is enabled by a high level on the STABLE input or a low level on the ASTABLE\ input, or both. The period of the square wave at the Q and Q\ Outputs in this mode of operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE\ input allow the circuit to be used as a gateable multivibrator. The OSCILLATOR output period will be half of the Q terminal output in the astable mode. However, a 50% duty cycle is not guaranteed at this output. The CD4047 triggers in the monostable mode when a positive-going edge occurs on the +TRIGGER-input while the -TRIGGER is held low. Input pulses may be of any duration relative to the output pulse. The CD4047-Series types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). check out : CD4094 - 8-Stage Shift and Store Bus Register IC Pinout: Pinout of CD4047 IC Applications: Digital equipment where low-power dissipation and/or high noise immunity are primary design requirements: Envelope detection Frequency multiplication Frequency division Frequency discriminators Timing circuits Time-delay applications

CD4049 - Hex Inverting Buffer/Converter IC The CD4x Series CD4049 hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. These devices feature logic-level conversion using only one supply voltage (VDD). The input signal level can exceed the VDD supply voltage when these devices are used for logic-level conversions. These devices are intended for use as hex buffers, CMOS to DTL/TTL converters, or as CMOS current drivers, and at VDD=5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range. check out : CD4504 - Hex Voltage Level Shifter IC Pinout: Pinout Of CD4049 IC Pin Name Pin # Type Description VDD 1 Power Supply Voltage (+3 to +15V) GND 8 Power Ground (0V) Q1-Q6 2, 4, 6, 10, 12, 15 Input Inputs to the inverters A1-A6 3, 5, 7, 9, 11, 14 Output Outputs from the inverters NC 13, 16 – Not Connected Applications: CMOS hex inverter/buffer CMOS to DTL/TTL hex converter CMOS current "sink" or "source" driver CMOS high-to-low logic level converter

CD4050 - Hex Non-Inverting Buffer IC The CD4050 hex buffers IC are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. These devices feature logic-level conversion using only one supply voltage (VDD). The input signal high level (VIH) can exceed the VDD supply voltage when these devices are used for logic-level conversions. These devices are intended for use as hex buffers IC, CMOS to DTL/ TTL converters, or as CMOS current drivers, and at VDD = 5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range. check out : CD4069 - Hex Inverter IC Pinout: Pinout of CD4050 - Hex Non-Inverting Buffer IC Applications: CMOS hex inverter/buffer. CMOS to DTL/TTL hex converter. CMOS current “sink” or “source” driver. CMOS HIGH-to-LOW logic level converter.

CD4051 - Single 8-channel Multiplexer/Demultiplexer IC The CD4051 analog multiplexers and demultiplexers IC are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full V DD – V SS and V DD – V EE supply-voltage ranges, independent of the logic state of the control signals. Pinout: Pinout of CD4051 Multiplexer/Demultiplexer IC

CD4052 - Differential 4-channel Multiplexer/Demultiplexer IC The CD4052 analog multiplexers/demultiplexers IC are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3?15V. For example, if VDD = 5V, VSS = 0V and VEE = ?5V, analog signals from ?5V to +5V can be controlled by digital inputs of 0?5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD?VSS and VDD?VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4052 is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. Pinout: Pinout of CD4052 - Differential 4-channel Multiplexer/Demultiplexer IC Pin Number Pin Name Description 16 Vdd Positive power input, maximum 20V 7 Vee Negative power rail, normally connected to ground. 8 Vss (Ground) Connected to ground of the circuit 6 INH Enable pin – Must be pulled to ground for normal operation 9,10 A,B Channel Select pins 1,12 Y0,X0 Channel 0 Input / Output 5,14 Y1,X1 Channel 1 Input / Output 2,15 Y2,X2 Channel 2 Input / Output 4,11 Y3,X3 Channel 3 Input / Output 3,13 Y,X Common Output / Input

CD4053 - Triple 2-channel Multiplexer/Demultiplexer IC The CD4053 IC analog multiplexers demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3?15V. For example, if VDD = 5V, VSS = 0V and VEE = ?5V, analog signals from ?5V to +5V can be controlled by digital inputs of 0?5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD?VSS and VDD?VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. The CD4x Series CD4053 Integrated Circuits is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels that are connected in a single-pole double-throw configuration. Pinout: Pin No Pin Name Description 1 Y1 Y1 Switch Input/Output 2 Y0 Y0 Switch Input/Output 3 Z1 Z1 Switch Input/Output 4 Z Input/Output Z 5 Z0 Z0 Switch Input/Output 6 INH Inhibit Input 7 VEE Emitter supply 8 VSS Source Supply 9 C Digital Control Input C 10 B Digital Control Input B 11 A Digital Control Input A 12 X0 X0 Switch Input/Output 13 X1 X1 Switch Input/Outputs 14 X Input/Output X 15 Y Input/Output Y 16 VDD Drain supply Applications: Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating